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SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
Rev. 06 -- 13 May 2008 Product data sheet
1. General description
The SC16IS740/750/760 is a slave I2C-bus/SPI interface to a single-channel high performance UART. It offers data rates up to 5 Mbit/s and guarantees low operating and sleeping current. The SC16IS750 and SC16IS760 also provide the application with 8 additional programmable I/O pins. The device comes in very small HVQFN24, TSSOP24 (SC16IS750/760) and TSSOP16 (SC16IS740) packages, which makes it ideally suitable for handheld, battery operated applications. This family of products enables seamless protocol conversion from I2C-bus or SPI to and RS-232/RS-485 and are fully bidirectional. The SC16IS760 differs from the SC16IS750 in that it supports SPI clock speeds up to 15 Mbit/s instead of the 4 Mbit/s supported by the SC16IS750, and in that it supports IrDA SIR up to 1.152 Mbit/s. In all other aspects, the SC16IS760 is functionally and electrically the same as the SC16IS750. The SC16IS740 is functionally and electrically identical to the SC16IS750, with the exception of the programmable I/O pins which are only present on the SC16IS750. The SC16IS740/750/760's internal register set is backward-compatible with the widely used and widely popular 16C450. This allows the software to be easily written or ported from another platform. The SC16IS740/750/760 also provides additional advanced features such as auto hardware and software flow control, automatic RS-485 support, and software reset. This allows the software to reset the UART at any moment, independent of the hardware reset signal.
2. Features
2.1 General features
I I I I I I I I I I I Single full-duplex UART Selectable I2C-bus or SPI interface 3.3 V or 2.5 V operation Industrial temperature range: -40 C to +95 C 64 bytes FIFO (transmitter and receiver) Fully compatible with industrial standard 16C450 and equivalent Baud rates up to 5 Mbit/s in 16x clock mode Auto hardware flow control using RTS/CTS Auto software flow control with programmable Xon/Xoff characters Single or double Xon/Xoff characters Automatic RS-485 support (automatic slave address detection)
NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
I I I I I I I I I I I
I I I I I
Up to eight programmable I/O pins (SC16IS750 and SC16IS760 only) RS-485 driver direction control via RTS signal RS-485 driver direction control inversion Built-in IrDA encoder and decoder interface SC16IS750 supports IrDA SIR with speeds up to 115.2 kbit/s SC16IS760 supports IrDA SIR with speeds up to 1.152 Mbit/s1 Software reset Transmitter and receiver can be enabled/disabled independent of each other Receive and Transmit FIFO levels Programmable special character detection Fully programmable character formatting N 5-bit, 6-bit, 7-bit or 8-bit character N Even, odd, or no parity N 1, 112, or 2 stop bits Line break generation and detection Internal Loopback mode Sleep current less than 30 A at 3.3 V Industrial and commercial temperature ranges Available in HVQFN24, TSSOP24 (SC16IS750/760) and TSSOP16 (SC16IS740) packages
2.2 I2C-bus features
I I I I Noise filter on SCL/SDA inputs 400 kbit/s maximum speed Compliant with I2C-bus fast speed Slave mode only
2.3 SPI features
I I I I SC16IS750 supports 4 Mbit/s maximum SPI clock speed SC16IS760 supports 15 Mbit/s maximum SPI clock speed Slave mode only SPI Mode 0
3. Applications
I Factory automation and process control I Portable and battery operated devices I Cellular data devices
1.
Please note that IrDA SIR at 1.152 Mbit/s is not compatible with IrDA MIR at that speed. Please refer to application notes for usage of IrDA SIR at 1.152 Mbit/s.
(c) NXP B.V. 2008. All rights reserved.
SC16IS740_750_760_6
Product data sheet
Rev. 06 -- 13 May 2008
2 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
4. Ordering information
Table 1. Ordering information Package Name SC16IS740IPW SC16IS750IBS SC16IS750IPW SC16IS760IBS SC16IS760IPW TSSOP16 HVQFN24 TSSOP24 HVQFN24 TSSOP24 Description plastic thin shrink small outline package; 16 leads; body width 4.4 mm plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm plastic thin shrink small outline package; 24 leads; body width 4.4 mm plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm plastic thin shrink small outline package; 24 leads; body width 4.4 mm Version SOT403-1 SOT616-3 SOT355-1 SOT616-3 SOT355-1 Type number
SC16IS740_750_760_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 13 May 2008
3 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
5. Block diagram
VDD
SC16IS750/760
RESET SCL SDA A0 A1 IRQ
1 k (3.3 V) 1.5 k (2.5 V) 4
I2C-BUS
16C450 COMPATIBLE REGISTER SETS
TX RX RTS CTS
VDD VDD I2C/SPI GPIO REGISTER
GPIO[3:0] GPIO4/DSR GPIO5/DTR GPIO6/CD GPIO7/RI
XTAL1
XTAL2
VSS
002aab014
Fig 1.
Block diagram of SC16IS750/760 I2C-bus interface
VDD
SC16IS740
RESET SCL SDA A0 A1 IRQ
1 k (3.3 V) 1.5 k (2.5 V)
I2C-BUS
16C450 COMPATIBLE REGISTER SETS
TX RX RTS CTS
VDD VDD I2C/SPI
XTAL1
XTAL2
VSS
002aab971
Fig 2.
Block diagram of SC16IS740 I2C-bus interface
SC16IS740_750_760_6
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Product data sheet
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SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
VDD
SC16IS750/760
RESET SCLK CS SO SI IRQ
1 k (3.3 V) 1.5 k (2.5 V) 4
SPI
16C450 COMPATIBLE REGISTER SETS
TX RX RTS CTS
VDD I2C/SPI GPIO REGISTER
GPIO[3:0] GPIO4/DSR GPIO5/DTR GPIO6/CD GPIO7/RI
XTAL1
XTAL2
VSS
002aab396
Fig 3.
Block diagram of SC16IS750/760 SPI interface
VDD
SC16IS740
RESET SCLK CS SO SI IRQ
1 k (3.3 V) 1.5 k (2.5 V)
SPI
16C450 COMPATIBLE REGISTER SETS
TX RX RTS CTS
VDD I2C/SPI
XTAL1
XTAL2
VSS
002aab972
Fig 4.
Block diagram of SC16IS740 SPI interface
SC16IS740_750_760_6
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Product data sheet
Rev. 06 -- 13 May 2008
5 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
6. Pinning information
6.1 Pinning
VDD A0 A1 n.c. SCL SDA IRQ I2C
1 2 3 4 5 6 7 8
002aab973
16 XTAL2 15 XTAL1 14 RESET 13 RX 12 TX 11 CTS 10 RTS 9 VSS
VDD CS SI SO SCLK VSS IRQ SPI
1 2 3 4 5 6 7 8
002aab974
16 XTAL2 15 XTAL1 14 RESET 13 RX 12 TX 11 CTS 10 RTS 9 VSS
SC16IS740IPW
SC16IS740IPW
a. I2C-bus interface Fig 5. Pin configuration for TSSOP16
b. SPI interface
CTS TX RX RESET XTAL1 XTAL2 VDD I2C A0
1 2 3 4 5 6 7 8 9
24 RTS 23 GPIO7/RI 22 GPIO6/CD 21 GPIO5/DTR 20 GPIO4/DSR 19 VSS 18 GPIO3 17 GPIO2 16 GPIO1 15 GPIO0 14 IRQ 13 SDA
002aab016
CTS TX RX RESET XTAL1 XTAL2 VDD SPI CS
1 2 3 4 5 6 7 8 9
24 RTS 23 GPIO7/RI 22 GPIO6/CD 21 GPIO5/DTR 20 GPIO4/DSR 19 VSS 18 GPIO3 17 GPIO2 16 GPIO1 15 GPIO0 14 IRQ 13 VSS
002aab399
SC16IS750IPW SC16IS760IPW
SC16IS750IPW SC16IS760IPW
A1 10 n.c. 11 SCL 12
SI 10 SO 11 SCLK 12
a. I2C-bus interface Fig 6. Pin configuration for TSSOP24
b. SPI interface
SC16IS740_750_760_6
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Product data sheet
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6 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
19 GPIO6/CD
23 TX
RESET XTAL1 XTAL2 VDD I2C A0
1 2 3 4 5 6 SDA 10 IRQ 11 GPIO0 12 7 8 9
18 GPIO5/DTR 17 GPIO4/DSR 16 VSS 15 GPIO3 14 GPIO2 13 GPIO1
RESET XTAL1 XTAL2 VDD SPI CS
1 2 3 4 5 6 VSS 10 IRQ 11 GPIO0 12 7 8 9
23 TX
terminal 1 index area
terminal 1 index area
19 GPIO6/CD 18 GPIO5/DTR 17 GPIO4/DSR 16 VSS 15 GPIO3 14 GPIO2 13 GPIO1
002aab401
(c) NXP B.V. 2008. All rights reserved.
20 GPIO7/RI
SC16IS750IBS SC16IS760IBS
SC16IS750IBS SC16IS760IBS
002aab015
Transparent top view
Transparent top view
a. I2C-bus interface Fig 7. Pin configuration for HVQFN24
b. SPI interface
6.2 Pin description
Table 2. Symbol CTS Pin description Pin TSSOP16 TSSOP24 HVQFN24 11 1 22 I UART clear to send (active LOW). A logic 0 (LOW) on the CTS pin indicates the modem or data set is ready to accept transmit data from the SC16IS740/750/760. Status can be tested by reading MSR[4]. This pin only affects the transmit and receive operations when auto CTS function is enabled via the Enhanced Feature Register EFR[7] for hardware flow control operation. UART transmitter output. During the local Loopback mode, the TX output pin is disabled and TX data is internally connected to the UART RX input. UART receiver input. During the local Loopback mode, the RX input pin is disabled and TX data is connected to the UART RX input internally. device hardware reset (active LOW)[1] Crystal input or external clock input. Functions as a crystal input or as an external clock input. A crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see Figure 15). Alternatively, an external clock can be connected to this pin. Crystal output or clock output. (See also XTAL1.) XTAL2 is used as a crystal oscillator output. power supply I2C-bus or SPI interface select. I2C-bus interface is selected if this pin is at logic HIGH. SPI interface is selected if this pin is at logic LOW. Type Description
TX
12
2
23
O
RX
13
3
24
I
RESET XTAL1
14 15
4 5
1 2
I I
XTAL2 VDD I2C/SPI
16 1 8
6 7 8
3 4 5
O I
SC16IS740_750_760_6
Product data sheet
Rev. 06 -- 13 May 2008
SCLK
n.c.
SI
SCL
SO
A1
20 GPIO7/RI
22 CTS
21 RTS
22 CTS
21 RTS
24 RX
24 RX
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NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
Table 2. Symbol CS/A0
Pin description ...continued Pin TSSOP16 TSSOP24 HVQFN24 2 9 6 I SPI chip select or I2C-bus device address select A0. If SPI configuration is selected by I2C/SPI pin, this pin is the SPI chip select pin (Schmitt-trigger, active LOW). If I2C-bus configuration is selected by I2C/SPI pin, this pin along with A1 pin allows user to change the device's base address. SPI data input pin or I2C-bus device address select A1. If SPI configuration is selected by I2C/SPI pin, this is the SPI data input pin. If I2C-bus configuration is selected by I2C/SPI pin, this pin along with A0 pin allows user to change the device's base address. To select the device address, please refer to Table 32. SPI data output pin. If SPI configuration is selected by I2C/SPI pin, this is a 3-stateable output pin. If I2C-bus configuration is selected by I2C/SPI pin, this pin function is undefined and must be left as n.c. (not connected). I2C-bus or SPI input clock. I2C-bus data input/output, open-drain if I2C-bus configuration is selected by I2C/SPI pin. If SPI configuration is selected then this pin is an undefined pin and must be connected to VSS. Interrupt (open-drain, active LOW). Interrupt is enabled when interrupt sources are enabled in the Interrupt Enable Register (IER). Interrupt conditions include: change of state of the input pins, receiver errors, available receiver buffer data, available transmit buffer space, or when a modem status flag is detected. An external resistor (1 k for 3.3 V, 1.5 k for 2.5 V) must be connected between this pin and VDD. programmable I/O pin programmable I/O pin programmable I/O pin programmable I/O pin programmable I/O pin or modem's DSR pin[2] programmable I/O pin or modem's DTR pin[2] programmable I/O pin or modem's CD pin[2] programmable I/O pin or modem's RI pin[2] UART request to send (active LOW). A logic 0 on the RTS pin indicates the transmitter has data ready and waiting to send. Writing a logic 1 in the modem control register MCR[1] will set this pin to a logic 0, indicating data is available. After a reset this pin is set to a logic 1. This pin only affects the transmit and receive operations when auto RTS function is enabled via the Enhanced Feature Register (EFR[6]) for hardware flow control operation. ground The center pad on the back side of the HVQFN24 package is metallic and should be connected to ground on the printed-circuit board. Type Description
SI/A1
3
10
7
I
SO
4
11
8
O
SCL/SCLK SDA
5 6
12 13
9 10
I I/O
IRQ
7
14
11
O
GPIO0 GPIO1 GPIO2 GPIO3
-
15 16 17 18 20 21 22 23 24
12 13 14 15 17 18 19 20 21
I/O I/O I/O I/O I/O I/O I/O I/O O
GPIO4/DSR GPIO5/DTR GPIO6/CD GPIO7/RI RTS 10
VSS VSS
9 -
19 -
16[3] center pad[3]
-
[1] [2]
See Section 7.4 "Hardware reset, Power-On Reset (POR) and software reset" Selectable with IOControl register bit 1.
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Product data sheet
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NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
[3]
HVQFN24 package die supply ground is connected to both VSS pins and exposed center pad. VSS pins must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region.
7. Functional description
The UART will perform serial-to-I2C conversion on data characters received from peripheral devices or modems, and I2C-to-serial conversion on data characters transmitted by the host. The complete status the SC16IS740/750/760 UART can be read at any time during functional operation by the host. The SC16IS740/750/760 can be placed in an alternate mode (FIFO mode) relieving the host of excessive software overhead by buffering received/transmitted characters. Both the receiver and transmitter FIFOs can store up to 64 characters (including three additional bits of error status per character for the receiver FIFO) and have selectable or programmable trigger levels. The SC16IS740/750/760 has selectable hardware flow control and software flow control. Hardware flow control significantly reduces software overhead and increases system efficiency by automatically controlling serial data flow using the RTS output and CTS input signals. Software flow control automatically controls data flow by using programmable Xon/Xoff characters. The UART includes a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and (216 - 1).
7.1 Trigger levels
The SC16IS740/750/760 provides independently selectable and programmable trigger levels for both receiver and transmitter interrupt generation. After reset, both transmitter and receiver FIFOs are disabled and so, in effect, the trigger level is the default value of one character. The selectable trigger levels are available via the FCR. The programmable trigger levels are available via the TLR. If TLR bits are cleared then selectable trigger level in FCR is used. If TLR bits are not cleared then programmable trigger level in TLR is used.
7.2 Hardware flow control
Hardware flow control is comprised of auto CTS and auto RTS (see Figure 8). Auto CTS and auto RTS can be enabled/disabled independently by programming EFR[7:6]. With auto CTS, CTS must be active before the UART can transmit data. Auto RTS only activates the RTS output when there is enough room in the FIFO to receive data and de-activates the RTS output when the RX FIFO is sufficiently full. The halt and resume trigger levels in the TCR determine the levels at which RTS is activated/deactivated. If TCR bits are cleared then selectable trigger levels in FCR are used in place of TCR. If both auto CTS and auto RTS are enabled, when RTS is connected to CTS, data transmission does not occur unless the receiver FIFO has empty space. Thus, overrun errors are eliminated during hardware flow control. If not enabled, overrun errors occur if the transmit data rate exceeds the receive FIFO servicing latency.
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Product data sheet
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NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
UART 1 SERIAL TO PARALLEL RX FIFO FLOW CONTROL RTS CTS
UART 2 PARALLEL TO SERIAL TX FIFO FLOW CONTROL
RX
TX
PARALLEL TO SERIAL TX FIFO FLOW CONTROL
TX
RX
SERIAL TO PARALLEL RX FIFO
CTS
RTS
FLOW CONTROL
002aab656
Fig 8.
Autoflow control (auto RTS and auto CTS) example
7.2.1 Auto RTS
Figure 9 shows RTS functional timing. The receiver FIFO trigger levels used in auto RTS are stored in the TCR or FCR. RTS is active if the RX FIFO level is below the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS is deasserted. The sending device (for example, another UART) may send an additional character after the trigger level is reached (assuming the sending UART has another character to send) because it may not recognize the deassertion of RTS until it has begun sending the additional character. RTS is automatically reasserted once the receiver FIFO reaches the resume trigger level programmed via TCR[7:4]. This reassertion allows the sending device to resume transmission.
RX
start
character N
stop
start
character N+1
stop
start
RTS
receive FIFO read
1
2
N
N+1
002aab040
(1) N = receiver FIFO trigger level. (2) The two blocks in dashed lines cover the case where an additional character is sent, as described in Section 7.2.1
Fig 9.
RTS functional timing
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Product data sheet
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NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
7.2.2 Auto CTS
Figure 10 shows CTS functional timing. The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, the transmitter sends the next byte. To stop the transmitter from sending the following byte, CTS must be deasserted before the middle of the last stop bit that is currently being sent. The auto CTS function reduces interrupts to the host system. When flow control is enabled, CTS level changes do not trigger host interrupts because the device automatically controls its own transmitter. Without auto CTS, the transmitter sends any data present in the transmit FIFO and a receiver overrun error may result.
TX
start
bit 0 to bit 7
stop
start
bit 0 to bit 7
stop
CTS
002aab041
(1) When CTS is LOW, the transmitter keeps sending serial data out. (2) When CTS goes HIGH before the middle of the last stop bit of the current character, the transmitter finishes sending the current character, but it does not send the next character. (3) When CTS goes from HIGH to LOW, the transmitter begins sending data again.
Fig 10. CTS functional timing
7.3 Software flow control
Software flow control is enabled through the enhanced feature register and the Modem Control Register. Different combinations of software flow control can be enabled by setting different combinations of EFR[3:0]. Table 3 shows software flow control options.
Table 3. EFR[3] 0 1 0 1 X X X 1 0 1 0 Software flow control options (EFR[3:0]) EFR[2] 0 0 1 1 X X X 0 1 1 0 EFR[1] X X X X 0 1 0 1 1 1 1 EFR[0] X X X X 0 0 1 1 1 1 1 TX, RX software flow control no transmit flow control transmit Xon1, Xoff1 transmit Xon2, Xoff2 transmit Xon1 and Xon2, Xoff1 and Xoff2 no receive flow control receiver compares Xon1, Xoff1 receiver compares Xon2, Xoff2 transmit Xon1, Xoff1 receiver compares Xon1 or Xon2, Xoff1 or Xoff2 transmit Xon2, Xoff2 receiver compares Xon1 or Xon2, Xoff1 or Xoff2 transmit Xon1 and Xon2, Xoff1 and Xoff2 receiver compares Xon1 and Xon2, Xoff1 and Xoff2 no transmit flow control receiver compares Xon1 and Xon2, Xoff1 and Xoff2
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Product data sheet
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SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
There are two other enhanced features relating to software flow control:
* Xon Any function (MCR[5]): Receiving any character will resume operation after
recognizing the Xoff character. It is possible that an Xon1 character is recognized as an Xon Any character, which could cause an Xon2 character to be written to the RX FIFO.
* Special character (EFR[5]): Incoming data is compared to Xoff2. Detection of the
special character sets the Xoff interrupt (IIR[4]) but does not halt transmission. The Xoff interrupt is cleared by a read of the IIR. The special character is transferred to the RX FIFO.
7.3.1 RX
When software flow control operation is enabled, the SC16IS740/750/760 will compare incoming data with Xoff1/Xoff2 programmed characters (in certain cases, Xoff1 and Xoff2 must be received sequentially). When the correct Xoff characters are received, transmission is halted after completing transmission of the current character. Xoff detection also sets IIR[4] (if enabled via IER[5]) and causes IRQ to go LOW. To resume transmission, an Xon1/Xon2 character must be received (in certain cases Xon1 and Xon2 must be received sequentially). When the correct Xon characters are received, IIR[4] is cleared, and the Xoff interrupt disappears.
7.3.2 TX
Xoff1/Xoff2 character is transmitted when the RX FIFO has passed the HALT trigger level programmed in TCR[3:0] or the selectable trigger level in FCR[7:6] Xon1/Xoff2 character is transmitted when the RX FIFO reaches the RESUME trigger level programmed in TCR[7:4] or RX FIFO falls below the lower selectable trigger level in FCR[7:6]. The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an ordinary character from the FIFO. This means that even if the word length is set to be 5, 6, or 7 bits, then the 5, 6, or 7 least significant bits of XOFF1/XOFF2 or XON1/XON2 will be transmitted. (Note that the transmission of 5, 6, or 7 bits of a character is seldom done, but this functionality is included to maintain compatibility with earlier designs.) It is assumed that software flow control and hardware flow control will never be enabled simultaneously. Figure 11 shows an example of software flow control.
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Product data sheet
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NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
UART1
UART2
TRANSMIT FIFO
RECEIVE FIFO
PARALLEL-TO-SERIAL
data
SERIAL-TO-PARALLEL
Xoff-Xon-Xoff SERIAL-TO-PARALLEL PARALLEL-TO-SERIAL
Xon1 WORD
Xon1 WORD
Xon2 WORD
Xon2 WORD
Xoff1 WORD
Xoff1 WORD
Xoff2 WORD
compare programmed Xon-Xoff characters
Xoff2 WORD
002aaa229
Fig 11. Example of software flow control
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NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
7.4 Hardware reset, Power-On Reset (POR) and software reset
These three reset methods are identical and will reset the internal registers as indicated in Table 4. Table 4 summarizes the state of register.
Table 4. Register Interrupt Enable Register Interrupt Identification Register FIFO Control Register Line Control Register Modem Control Register Line Status Register Modem Status Register Enhanced Feature Register Receiver Holding Register Transmitter Holding Register Transmission Control Register Trigger Level Register Transmit FIFO level Receive FIFO level I/O direction[2] I/O interrupt I/O control[3] enable[2] Register reset[1] Reset state all bits cleared bit 0 is set; all other bits cleared all bits cleared reset to 0001 1101 (0x1D) all bits cleared bit 5 and bit 6 set; all other bits cleared bits 0:3 cleared; bits 4:7 input signals all bits cleared pointer logic cleared pointer logic cleared all bits cleared. all bits cleared. reset to 0100 0000 (0x40) all bits cleared all bits cleared all bits cleared all bits cleared all bits cleared
Extra Feature Register
[1] [2] [3]
Registers DLL, DLH, SPR, XON1, XON2, XOFF1, XOFF2 are not reset by the top-level reset signal RESET, POR or Software Reset, that is, they hold their initialization values during reset. This register is not supported in SC16IS740. Only UART Software Reset bit is supported in this register.
Table 5 summarizes the state of registers after reset.
Table 5. Signal TX RTS I/Os IRQ Output signals after reset Reset state HIGH HIGH inputs HIGH by external pull-up
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Product data sheet
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NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
7.5 Interrupts
The SC16IS740/750/760 has interrupt generation and prioritization (seven prioritized levels of interrupts) capability. The interrupt enable registers (IER and IOIntEna) enable each of the seven types of interrupts and the IRQ signal in response to an interrupt generation. When an interrupt is generated, the IIR indicates that an interrupt is pending and provides the type of interrupt through IIR[5:0]. Table 6 summarizes the interrupt control functions.
Table 6. IIR[5:0] 00 0001 00 0110 00 1100 00 0100 00 0010 00 0000 11 0000 01 0000 10 0000
[1]
Summary of interrupt control functions Priority level none 1 2 2 3 4 5 6 7 Interrupt type none receiver line status RX time-out RHR interrupt THR interrupt modem status[1] I/O pins[1] Xoff interrupt CTS, RTS Interrupt source none OE, FE, PE, or BI errors occur in characters in the RX FIFO Stale data in RX FIFO Receive data ready (FIFO disable) or RX FIFO above trigger level (FIFO enable) Transmit FIFO empty (FIFO disable) or TX FIFO passes above trigger level (FIFO enable) Change of state of modem input pins Input pins change of state Receive Xoff character(s)/ special character RTS pin or CTS pin change state from active (LOW) to inactive (HIGH)
Available only on SC16IS750/SC16IS760.
It is important to note that for the framing error, parity error, and break conditions, LSR[7] generates the interrupt. LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only when there are no more errors remaining in the FIFO. LSR[4:2] always represent the error status for the received character at the top of the RX FIFO. Reading the RX FIFO updates LSR[4:2] to the appropriate status for the new character at the top of the FIFO. If the RX FIFO is empty, then LSR[4:2] are all zeros. For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt is cleared by an Xon flow character detection. If a special character detection caused the interrupt, the interrupt is cleared by a read of the IIR.
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Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
7.5.1 Interrupt mode operation
In Interrupt mode (if any bit of IER[3:0] is 1) the host is informed of the status of the receiver and transmitter by an interrupt signal, IRQ. Therefore, it is not necessary to continuously poll the Line Status Register (LSR) to see if any interrupt needs to be serviced. Figure 12 shows Interrupt mode operation.
read IIR IRQ HOST
IIR
IER 1 1 1 1
THR
RHR
002aab042
Fig 12. Interrupt mode operation
7.5.2 Polled mode operation
In Polled mode (IER[3:0] = 0000) the status of the receiver and transmitter can be checked by polling the Line Status Register (LSR). This mode is an alternative to the FIFO Interrupt mode of operation where the status of the receiver and transmitter is automatically known by means of interrupts sent to the CPU. Figure 13 shows FIFO Polled mode operation.
read LSR HOST
LSR
IER 0 0 0 0
THR
RHR
002aab043
Fig 13. FIFO Polled mode operation
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7.6 Sleep mode
Sleep mode is an enhanced feature of the SC16IS740/750/760 UART. It is enabled when EFR[4], the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered when:
* The serial data input line, RX, is idle (see Section 7.7 "Break and time-out
conditions").
* The TX FIFO and TX shift register are empty. * There are no interrupts pending except THR.
Remark: Sleep mode will not be entered if there is data in the RX FIFO. In Sleep mode, the clock to the UART is stopped. Since most registers are clocked using these clocks, the power consumption is greatly reduced. The UART will wake up when any change is detected on the RX line, when there is any change in the state of the modem input pins, or if data is written to the TX FIFO. Remark: Writing to the divisor latches, DLL and DLH, to set the baud clock, must not be done during Sleep mode. Therefore, it is advisable to disable Sleep mode using IER[4] before writing to DLL or DLH.
7.7 Break and time-out conditions
When the UART receives a number of characters and these data are not enough to set off the receive interrupt (because they do not reach the receive trigger level), the UART will generate a time-out interrupt instead, 4 character times after the last character is received. The time-out counter will be reset at the center of each stop bit received or each time the receive FIFO is read. A break condition is detected when the RX pin is pulled LOW for a duration longer than the time it takes to send a complete character plus Start, Stop and Parity bits. A break condition can be sent by setting LCR[6]. When this happens the TX pin will be pulled LOW until LSR[6] is cleared by the software.
7.8 Programmable baud rate generator
The SC16IS740/750/760 UART contains a programmable baud rate generator that takes any clock input and divides it by a divisor in the range between 1 and (216 - 1). An additional divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in Figure 14. The output frequency of the baud rate generator is 16 x the baud rate. The formula for the divisor is given in Equation 1: XTAL1 crystal input frequency ------------------------------------------------------------------------------------ - prescaler divisor = ----------------------------------------------------------------------------------------desired baud rate x 16 where: prescaler = 1, when MCR[7] is set to `0' after reset (divide-by-1 clock selected) prescaler = 4, when MCR[7] is set to `1' after reset (divide-by-4 clock selected). Remark: The default value of prescaler after reset is divide-by-1.
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Figure 14 shows the internal prescaler and baud rate generator circuitry.
PRESCALER LOGIC (DIVIDE-BY-1) XTAL1 XTAL2 INTERNAL OSCILLATOR LOGIC
MCR[7] = 0 internal baud rate clock for transmitter and receiver
input clock reference clock MCR[7] = 1
BAUD RATE GENERATOR LOGIC
PRESCALER LOGIC (DIVIDE-BY-4)
002aaa233
Fig 14. Prescaler and baud rate generator block diagram
DLL and DLH must be written to in order to program the baud rate. DLL and DLH are the least significant and most significant byte of the baud rate divisor. If DLL and DLH are both zero, the UART is effectively disabled, as no baud clock will be generated. Remark: The programmable baud rate generator is provided to select both the transmit and receive clock rates. Table 7 and Table 8 show the baud rate and divisor correlation for crystal with frequency 1.8432 MHz and 3.072 MHz, respectively. Figure 15 shows the crystal clock circuit reference.
Table 7. Baud rates using a 1.8432 MHz crystal Divisor used to generate 16x clock 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 Percent error difference between desired and actual 0 0 0.026 0.058 0 0 0 0 0 0.69 0 0 0 0 0 0 0 2.86
Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000
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Baud rates using a 3.072 MHz crystal Divisor used to generate 16x clock 2304 2560 1745 1428 1280 640 320 160 107 96 80 53 40 27 20 10 5 Percent error difference between desired and actual 0 0 0.026 0.034 0 0 0 0 0.312 0 0 0.628 0 1.23 0 0 0
Table 8.
Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400
XTAL1
XTAL2
1.8432 MHz
C1 22 pF
C2 33 pF
002aab402
Fig 15. Crystal oscillator circuit reference
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8. Register descriptions
The programming combinations for register selection are shown in Table 9.
Table 9. RHR/THR IER IIR/FCR LCR MCR LSR MSR SPR TCR TLR TXLVL RXLVL IODir[3] IOState[3] IOIntEna[3] IOControl[3] EFCR DLL DLH EFR XON1 XON2 XOFF1 XOFF2
[1] [2] [3] [4] [5]
Register map - read/write properties Write mode Transmit Holding Register (THR) Interrupt Enable Register FIFO Control Register (FCR) Line Control Register Modem Control Register[1] n/a n/a Scratchpad Register (TCR)[2] Transmission Control Register[2] Trigger Level Register[2] n/a n/a I/O pin Direction Register n/a I/O Interrupt Enable Register I/O pins Control Register Extra Features Register divisor latch LSB[4] divisor latch MSB[4] Enhanced Feature Register[5] Xon1 word[5] Xon2 word[5] Xoff1 word[5] Xoff2 word[5] Receive Holding Register (RHR) Interrupt Enable Register (IER) Interrupt Identification Register (IIR) Line Control Register (LCR) Modem Control Register (MCR)[1] Line Status Register (LSR) Modem Status Register (MSR) Scratchpad Register (SPR) Transmission Control Register Trigger Level Register (TLR)[2] Transmit FIFO Level Register Receive FIFO Level Register I/O pin Direction Register I/O pin States Register I/O Interrupt Enable Register I/O pins Control Register Extra Features Register divisor latch LSB (DLL)[4] divisor latch MSB (DLH)[4] Enhanced Feature Register (EFR)[5] Xon1 word[5] Xon2 word[5] Xoff1 word[5] Xoff2 word[5]
Register name Read mode
MCR[7] can only be modified when EFR[4] is set. Accessible only when ERF[4] = 1 and MCR[2] = 1, that is, EFR[4] and MCR[2] are read/write enables. Available only on SC16IS750/SC16IS760. Accessible only when LCR[7] is logic 1. Accessible only when LCR is set to 1011 1111b (0xBF).
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Table 10. Register address 0x00 0x00 0x01
SC16IS740/750/760 internal registers Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W
General register set[1] RHR THR IER bit 7 bit 7 CTS interrupt enable[2] RX trigger level (MSB) bit 6 bit 6 RTS interrupt enable[2] RX trigger level (LSB) bit 5 bit 5 Xoff[2] bit 4 bit 4 Sleep mode[2] bit 3 bit 3 bit 2 bit 2 bit 1 bit 1 bit 0 bit 0 RX data available interrupt FIFO enable R W R/W
modem status receive line THR empty interrupt status interrupt interrupt reserved[3] interrupt priority bit 2 parity enable reserved[3] TX FIFO reset[5] interrupt priority bit 1 stop bit TCR and TLR enable[2] parity error RI/(IO7)[4] bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 reserved[3] RX FIFO reset[5] interrupt priority bit 0 word length bit 1 RTS overrun error DSR/ (IO4)[4] bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 reserved[3]
0x02 0x02 0x03 0x04 0x05 0x06 0x07 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
FCR IIR[6] LCR MCR LSR MSR SPR TCR[7] TLR[7] TXLVL RXLVL IODir[4] IOState[4] IOIntEna[4] reserved[3]
TX trigger TX trigger level (MSB)[2] level (LSB)[2] interrupt interrupt priority bit 4[2] priority bit 3[2] set parity Xon Any[2] THR empty DSR/ (IO4)[4] bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 bit 5 reserved[3] reserved[3] auto RS-485 RTS output inversion even parity loopback enable
W
FIFO enable FIFO enable Divisor Latch set break Enable clock divisor[2] FIFO data error CD/(IO6)[4] bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 bit 7 reserved[3] IrDA mode enable[2] THR and TSR empty RI/(IO7)[4] bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 bit 6 reserved[3] reserved[3]
interrupt status R word length bit 0 DTR/(IO5)[4] R/W
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
R/W
break interrupt framing error CTS bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 bit 4 reserved[3] reserved[3] auto RS-485 RTS direction control CD/ (IO6)[4] bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 bit 3 reserved[3]
data in receiver R CTS bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 reserved[3] R/W R/W R R/W R/W R/W R R R/W R/W R/W
SC16IS740/750/760
IOControl[4] reserved[3] EFCR
UART reserved[3] software reset reserved[3] transmitter disable
I/O[7:4] or RI, latch CD, DTR, DSR receiver disable 9-bit mode enable
reserved[3] IrDA mode (slow/ fast)[8]
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Table 10. Register address 0x00 0x01 0x02 SC16IS740/750/760 internal registers ...continued Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W
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Special register set[9] DLL DLH EFR bit 7 bit 7 set[10] Auto CTS Auto RTS special character detect bit 5 bit 5 bit 5 bit 5 enable enhanced functions bit 4 bit 4 bit 4 bit 4 software flow control bit 3 bit 3 bit 3 bit 3 bit 3 software flow control bit 2 bit 2 bit 2 bit 2 bit 2 software flow control bit 1 bit 1 bit 1 bit 1 bit 1 software flow control bit 0 bit 0 bit 0 bit 0 bit 0 R/W bit 6 bit 6 bit 5 bit 5 bit 4 bit 4 bit 3 bit 3 bit 2 bit 2 bit 1 bit 1 bit 0 bit 0 R/W R/W
Enhanced register
0x04 0x05 0x06 0x07
[1] [2] [3] [4] [5] [6] [7] [8] [9]
XON1 XON2 XOFF1 XOFF2
bit 7 bit 7 bit 7 bit 7
bit 6 bit 6 bit 6 bit 6
R/W R/W R/W R/W
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
These registers are accessible only when LCR[7] = 0. These bits in can only be modified if register bit EFR[4] is enabled. These bits are reserved and should be set to 0. Only available on the SC16IS750/SC16IS760. After Receive FIFO or Transmit FIFO reset (through FCR[1:0]), the user must wait at least 2 x Tclk of XTAL1 before reading or writing data to RHR and THR, respectively. Burst reads on the serial interface (that is, reading multiple elements on the I2C-bus without a STOP or repeated START condition, or reading multiple elements on the SPI bus without de-asserting the CS pin), should not be performed on the IIR register. These registers are accessible only when MCR[2] = 1 and EFR[4] = 1. IrDA mode slow/fast for SC16IS760, slow only for SC16IS750. The special register set is accessible only when LCR[7] = 1 and not 0xBF.
SC16IS740/750/760
[10] Enhanced Feature Registers are only accessible when LCR = 0xBF.
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8.1 Receive Holding Register (RHR)
The receiver section consists of the Receiver Holding Register (RHR) and the Receiver Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data from the RX pin. The data is converted to parallel data and moved to the RHR. The receiver section is controlled by the Line Control Register. If the FIFO is disabled, location zero of the FIFO is used to store the characters.
8.2 Transmit Holding Register (THR)
The transmitter section consists of the Transmit Holding Register (THR) and the Transmit Shift Register (TSR). The THR is actually a 64-byte FIFO. The THR receives data and shifts it into the TSR, where it is converted to serial data and moved out on the TX pin. If the FIFO is disabled, the FIFO is still used to store the byte. Characters are lost if overflow occurs.
8.3 FIFO Control Register (FCR)
This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting transmitter and receiver trigger levels. Table 11 shows FIFO Control Register bit settings.
Table 11. Bit 7:6 FIFO Control Register bits description Description
Symbol
FCR[7] (MSB), RX trigger. Sets the trigger level for the RX FIFO. FCR[6] (LSB) 00 = 8 characters 01 = 16 characters 10 = 56 characters 11 = 60 characters
5:4
FCR[5] (MSB), TX trigger. Sets the trigger level for the TX FIFO. FCR[4] (LSB) 00 = 8 spaces 01 = 16 spaces 10 = 32 spaces 11 = 56 spaces FCR[5:4] can only be modified and enabled when EFR[4] is set. This is because the transmit trigger level is regarded as an enhanced function.
3 2
FCR[3] FCR[2][1]
reserved reset TX FIFO logic 0 = no FIFO transmit reset (normal default condition) logic 1 = clears the contents of the transmit FIFO and resets the FIFO level logic (the Transmit Shift Register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO.
1
FCR[1][1]
reset RX FIFO logic 0 = no FIFO receive reset (normal default condition) logic 1 = clears the contents of the receive FIFO and resets the FIFO level logic (the Receive Shift Register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO.
0
FCR[0]
FIFO enable logic 0 = disable the transmit and receive FIFO (normal default condition) logic 1 = enable the transmit and receive FIFO
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[1]
FIFO reset requires at least two XTAL1 clocks, therefore, they cannot be reset without the presence of the XTAL1 clock.
8.4 Line Control Register (LCR)
This register controls the data communication format. The word length, number of stop bits, and parity type are selected by writing the appropriate bits to the LCR. Table 12 shows the Line Control Register bit settings.
Table 12. Bit 7 Line Control Register bits description Symbol LCR[7] Description divisor latch enable logic 0 = divisor latch disabled (normal default condition) logic 1 = divisor latch enabled 6 LCR[6] Break control bit. When enabled, the break control bit causes a break condition to be transmitted (the TX output is forced to a logic 0 state). This condition exists until disabled by setting LCR[6] to a logic 0. logic 0 = no TX break condition (normal default condition). logic 1 = forces the transmitter output (TX) to a logic 0 to alert the communication terminal to a line break condition 5 LCR[5] Set parity. LCR[5] selects the forced parity format (if LCR[3] = 1). logic 0 = parity is not forced (normal default condition). LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1 for the transmit and receive data. LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0 for the transmit and receive data. 4 LCR[4] parity type select logic 0 = odd parity is generated (if LCR[3] = 1) logic 1 = even parity is generated (if LCR[3] = 1) 3 LCR[3] parity enable logic 0 = no parity (normal default condition). logic 1 = a parity bit is generated during transmission and the receiver checks for received parity 2 LCR[2] Number of stop bits. Specifies the number of stop bits. 0 to 1 stop bit (word length = 5, 6, 7, 8) 1 to 1.5 stop bits (word length = 5) 1 = 2 stop bits (word length = 6, 7, 8) 1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be transmitted or received; see Table 15.
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LCR[5] parity selection LCR[4] X 0 1 0 1 LCR[3] 0 1 1 1 1 Parity selection no parity odd parity even parity forced parity `1' forced parity `0'
Table 13. LCR[5] X 0 0 1 1 Table 14. LCR[2] 0 1 1 Table 15. LCR[1] 0 0 1 1
LCR[2] stop bit length Word length (bits) 5, 6, 7, 8 5 6, 7, 8 LCR[1:0] word length LCR[0] 0 1 0 1 Word length (bits) 5 6 7 8 Stop bit length (bit times) 1 112 2
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8.5 Line Status Register (LSR)
Table 16 shows the Line Status Register bit settings.
Table 16. Bit 7 Line Status Register bits description Description FIFO data error. logic 0 = no error (normal default condition) logic 1 = at least one parity error, framing error, or break indication is in the receiver FIFO. This bit is cleared when no more errors are present in the FIFO. 6 LSR[6] THR and TSR empty. This bit is the Transmit Empty indicator. logic 0 = transmitter hold and shift registers are not empty logic 1 = transmitter hold and shift registers are empty 5 LSR[5] THR empty. This bit is the Transmit Holding Register Empty indicator. logic 0 = transmit hold register is not empty logic 1 = transmit hold register is empty. The host can now load up to 64 characters of data into the THR if the TX FIFO is enabled. 4 LSR[4] break interrupt logic 0 = no break condition (normal default condition) logic 1 = a break condition occurred and associated character is 0x00, that is, RX was LOW for one character time frame 3 LSR[3] framing error logic 0 = no framing error in data being read from RX FIFO (normal default condition). logic 1 = framing error occurred in data being read from RX FIFO, that is, received data did not have a valid stop bit 2 LSR[2] parity error. logic 0 = no parity error (normal default condition) logic 1 = parity error in data being read from RX FIFO 1 LSR[1] overrun error logic 0 = no overrun error (normal default condition) logic 1 = overrun error has occurred 0 LSR[0] data in receiver logic 0 = no data in receive FIFO (normal default condition) logic 1 = at least one character in the RX FIFO
Symbol LSR[7]
When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the top of the RX FIFO (next character to be read). Therefore, errors in a character are identified by reading the LSR and then reading the RHR. LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only when there are no more errors remaining in the FIFO.
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8.6 Modem Control Register (MCR)
The MCR controls the interface with the mode, data set, or peripheral device that is emulating the modem. Table 17 shows the Modem Control Register bit settings.
Table 17. Bit 7 Modem Control Register bits description Symbol MCR[7][1] Description clock divisor logic 0 = divide-by-1 clock input logic 1 = divide-by-4 clock input 6 MCR[6][1] IrDA mode enable logic 0 = normal UART mode logic 1 = IrDA mode 5 MCR[5][1] Xon Any logic 0 = disable Xon Any function logic 1 = enable Xon Any function 4 MCR[4] enable loopback logic 0 = normal operating mode logic 1 = enable local Loopback mode (internal). In this mode the MCR[1:0] signals are looped back into MSR[4:5] and the TX output is looped back to the RX input internally. 3 2 MCR[3] MCR[2] reserved TCR and TLR enable logic 0 = disable the TCR and TLR register. logic 1 = enable the TCR and TLR register. 1 MCR[1] RTS logic 0 = force RTS output to inactive (HIGH) logic 1 = force RTS output to active (LOW). In Loopback mode, controls MSR[4]. If Auto RTS is enabled, the RTS output is controlled by hardware flow control. 0 MCR[0] DTR[2]. If GPIO5 is selected as DTR modem pin through IOControl register bit 1, the state of DTR pin can be controlled as below. Writing to IOState bit 5 will not have any effect on this pin. logic 0 = Force DTR output to inactive (HIGH) logic 1 = Force DTR output to active (LOW)
[1] [2] MCR[7:5] and MCR[2] can only be modified when EFR[4] is set, that is, EFR[4] is a write enable. Only available on SC16IS750/SC16IS760.
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8.7 Modem Status Register (MSR)
This 8-bit register provides information about the current state of the control lines from the modem, data set, or peripheral device to the host. It also indicates when a control input from the modem changes state. Table 18 shows Modem Status Register bit settings.
Table 18. Bit 7 Modem Status Register bits description Description CD[1] (active HIGH, logical 1). If GPIO6 is selected as CD modem pin through IOControl register bit 1, the state of CD pin can be read from this bit. This bit is the complement of the CD input. Reading IOState bit 6 does not reflect the true state of CD pin. RI[1] (active HIGH, logical 1). If GPIO7 is selected as RI modem pin through IOControl register bit 1, the state of RI pin can be read from this bit. This bit is the complement of the RI input. Reading IOState bit 6 does not reflect the true state of RI pin. DSR[1] (active HIGH, logical 1). If GPIO4 is selected as DSR modem pin through IOControl register bit 1, the state of DSR pin can be read from this bit. This bit is the complement of the DSR input. Reading IOState bit 4 does not reflect the true state of DSR pin. CTS (active HIGH, logical 1). This bit is the complement of the CTS input. CD[1]. Indicates that CD input has changed state. Cleared on a read. RI[1]. Indicates that RI input has changed state from LOW to HIGH. Cleared on a read. DSR[1]. Indicates that DSR input has changed state. Cleared on a read. CTS. Indicates that CTS input has changed state. Cleared on a read.
Symbol MSR[7]
6
MSR[6]
5
MSR[5]
4 3 2 1 0
[1]
MSR[4] MSR[3] MSR[2] MSR[1] MSR[0]
Only available on SC16IS750/SC16IS760.
Remark: The primary inputs RI, CD, CTS, DSR are all active LOW.
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8.8 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver error, RHR interrupt, THR interrupt, modem status, Xoff received, or CTS/RTS change of state from LOW to HIGH. The IRQ output signal is activated in response to interrupt generation. Table 19 shows the Interrupt Enable Register bit settings.
Table 19. Bit 7 Interrupt Enable Register bits description Description CTS interrupt enable logic 0 = disable the CTS interrupt (normal default condition) logic 1 = enable the CTS interrupt 6 IER[6][1] RTS interrupt enable logic 0 = disable the RTS interrupt (normal default condition) logic 1 = enable the RTS interrupt 5 IER[5][1] Xoff interrupt logic 0 = disable the Xoff interrupt (normal default condition) logic 1 = enable the Xoff interrupt 4 IER[4][1] Sleep mode logic 0 = disable Sleep mode (normal default condition) logic 1 = enable Sleep mode. See Section 7.6 "Sleep mode" for details. 3 IER[3] Modem Status Interrupt[2]. logic 0 = disable the modem status register interrupt (normal default condition) logic 1 = enable the modem status register interrupt Remark: See IOControl register bit 1 in Table 30 for the description of how to program the pins as modem pins. 2 IER[2] Receive Line Status interrupt logic 0 = disable the receiver line status interrupt (normal default condition) logic 1 = enable the receiver line status interrupt 1 IER[1] Transmit Holding Register interrupt. logic 0 = disable the THR interrupt (normal default condition) logic 1 = enable the THR interrupt 0 IER[0] Receive Holding Register interrupt. logic 0 = disable the RHR interrupt (normal default condition) logic 1 = enable the RHR interrupt
[1] [2] IER[7:4] can only be modified if EFR[4] is set, that is, EFR[4] is a write enable. Re-enabling IER[1] will not cause a new interrupt if the THR is below the threshold. Only available on the SC16IS750/SC16IS760.
Symbol IER[7][1]
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8.9 Interrupt Identification Register (IIR)
The IIR is a read-only 8-bit register which provides the source of the interrupt in a prioritized manner. Table 20 shows Interrupt Identification Register bit settings.
Table 20. Bit 7:6 5:1 0 Interrupt Identification Register bits description Symbol IIR[7:6] IIR[5:1] IIR[0] Description mirror the contents of FCR[0] 5-bit encoded interrupt. See Table 21. interrupt status logic 0 = an interrupt is pending logic 1 = no interrupt is pending Table 21. Priority level 1 2 2 3 4 5 6 7 Interrupt source IIR[5] 0 0 0 0 0 1 0 1 IIR[4] 0 0 0 0 0 1 1 0 IIR[3] 0 1 0 0 0 0 0 0 IIR[2] 1 1 1 0 0 0 0 0 IIR[1] 1 0 0 1 0 0 0 0 IIR[0] 0 0 0 0 0 0 0 0 Source of the interrupt Receiver Line Status error Receiver time-out interrupt RHR interrupt THR interrupt modem interrupt[1][2] input pin change of state[1][2] received Xoff signal/ special character CTS, RTS change of state from active (LOW) to inactive (HIGH)
[1] [2]
Modem interrupt status must be read via MSR register and GPIO interrupt status must be read via IOState register. Only available on SC16IS750/SC16IS760.
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8.10 Enhanced Features Register (EFR)
This 8-bit register enables or disables the enhanced features of the UART. Table 22 shows the enhanced feature register bit settings.
Table 22. Bit 7 Enhanced Features Register bits description Description CTS flow control enable logic 0 = CTS flow control is disabled (normal default condition) logic 1 = CTS flow control is enabled. Transmission will stop when a HIGH signal is detected on the CTS pin. 6 EFR[6] RTS flow control enable. logic 0 = RTS flow control is disabled (normal default condition) logic 1 = RTS flow control is enabled. The RTS pin goes HIGH when the receiver FIFO halt trigger level TCR[3:0] is reached, and goes LOW when the receiver FIFO resume transmission trigger level TCR[7:4] is reached. 5 EFR[5] Special character detect logic 0 = Special character detect disabled (normal default condition) logic 1 = Special character detect enabled. Received data is compared with Xoff2 data. If a match occurs, the received data is transferred to FIFO and IIR[4] is set to a logical 1 to indicate a special character has been detected. 4 EFR[4] Enhanced functions enable bit logic 0 = disables enhanced functions and writing to IER[7:4], FCR[5:4], MCR[7:5]. logic 1 = enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5] so that they can be modified. 3:0 EFR[3:0] Combinations of software flow control can be selected by programming these bits. See Table 3 "Software flow control options (EFR[3:0])".
Symbol EFR[7]
8.11 Division registers (DLL, DLH)
These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock in the baud rate generator. DLH stores the most significant part of the divisor. DLL stores the least significant part of the divisor. Remark: DLL and DLH can only be written to before Sleep mode is enabled, that is, before IER[4] is set.
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8.12 Transmission Control Register (TCR)
This 8-bit register is used to store the RX FIFO threshold levels to stop/start transmission during hardware/software flow control. Table 23 shows Transmission Control Register bit settings.
Table 23. Bit 7:4 3:0 Transmission Control Register bits description Symbol TCR[7:4] TCR[3:0] Description RX FIFO trigger level to resume RX FIFO trigger level to halt transmission
TCR trigger levels are available from 0 to 60 characters with a granularity of four. Remark: TCR can only be written to when EFR[4] = 1 and MCR[2] = 1. The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is no built-in hardware check to make sure this condition is met. Also, the TCR must be programmed with this condition before auto RTS or software flow control is enabled to avoid spurious operation of the device.
8.13 Trigger Level Register (TLR)
This 8-bit register is used to store the transmit and received FIFO trigger levels used for interrupt generation. Trigger levels from 4 to 60 can be programmed with a granularity of 4. Table 24 shows trigger level register bit settings.
Table 24. Bit 7:4 3:0 Trigger Level Register bits description Symbol TLR[7:4] TLR[3:0] Description RX FIFO trigger levels (4 to 60), number of characters available. TX FIFO trigger levels (4 to 60), number of spaces available.
Remark: TLR can only be written to when EFR[4] = 1 and MCR[2] = 1. If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the FIFO Control Register (FCR) are used for the transmit and receive FIFO trigger levels. Trigger levels from 4 characters to 60 characters are available with a granularity of four. The TLR should be programmed for N4, where N is the desired trigger level. When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the trigger level setting defined in FCR. If TLR has non-zero trigger level value, the trigger level defined in FCR is discarded. This applies to both transmit FIFO and receive FIFO trigger level setting. When TLR is used for RX trigger level control, FCR[7:6] should be left at the default state, that is, `00'.
8.14 Transmitter FIFO Level register (TXLVL)
This register is a read-only register, it reports the number of spaces available in the transmit FIFO.
Table 25. Bit 7 6:0
SC16IS740_750_760_6
Transmitter FIFO Level register bits description Symbol TXLVL[6:0] Description not used; set to zeros number of spaces available in TX FIFO, from 0 (0x00) to 64 (0x40)
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8.15 Receiver FIFO Level register (RXLVL)
This register is a read-only register, it reports the fill level of the receive FIFO. That is, the number of characters in the RX FIFO.
Table 26. Bit 7 6:0 Receiver FIFO Level register bits description Symbol RXLVL[6:0] Description not used; set to zeros number of characters stored in RX FIFO, from 0 (0x00) to 64 (0x40)
8.16 Programmable I/O pins Direction register (IODir)
This register is only available on the SC16IS750 and SC16IS760. This register is used to program the I/O pins direction. Bit 0 to bit 7 controls GPIO0 to GPIO7.
Table 27. Bit 7:0 IODir register bits description Symbol IODir Description set GPIO pins [7:0] to input or output 0 = input 1 = output
Remark: If there is a pending input (GPIO) interrupt and IODir is written, this pending interrupt will be cleared, that is, the interrupt signal will be negated.
8.17 Programmable I/O pins State Register (IOState)
This register is only available on the SC16IS750 and SC16IS760. When `read', this register returns the actual state of all I/O pins. When `write', each register bit will be transferred to the corresponding IO pin programmed as output.
Table 28. Bit 7:0 IOState register bits description Symbol IOState Description Write this register: set the logic level on the output pins 0 = set output pin to zero 1 = set output pin to one Read this register: return states of all pins
8.18 I/O Interrupt Enable Register (IOIntEna)
This register is only available on the SC16IS750 and SC16IS760. This register enables the interrupt due to a change in the I/O configured as inputs. If GPIO[7:4] are programmed as modem pins, their interrupt generation must be enabled via IER register bit 3. In this case bit 7 to bit 4 of IOIntEna will have no effect on GPIO[7:4].
Table 29. Bit 7:0 IOIntEna register bits description Symbol IOIntEna Description input interrupt enable 0 = a change in the input pin will not generate an interrupt 1 = a change in the input will generate an interrupt
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8.19 I/O Control register (IOControl)
This register is only available on the SC16IS750 and SC16IS760.
Table 30. Bit 7:4 3 IOControl register bits description Symbol SRESET Description reserved for future use software reset A write to bit will reset the device. Once the device is reset this bit is automatically set to `0' 2 1 GPIO[7:4] or modem pins reserved for future use This bit programs GPIO[7:4] as I/O pins or modem RI, CD, DTR, DSR pins. 0 = GPIO[7:4] behave as I/O pins 1 = GPIO[7:4] behave as RI, CD, DTR, DSR 0 IOLATCH enable/disable inputs latching 0 = input values are not latched. A change in any input generates an interrupt. A read of the input register clears the interrupt. If the input goes back to its initial logic state before the input register is read, then the interrupt is cleared. 1 = input values are latched. A change in the input generates an interrupt and the input logic value is loaded in the bit of the corresponding input state register (IOState). A read of the IOState register clears the interrupt. If the input pin goes back to its initial logic state before the interrupt register is read, then the interrupt is not cleared and the corresponding bit of the IOState register keeps the logic value that initiates the interrupt.
Remark: As I/O pins, the direction, state, and interrupt of GPIO4 to GPIO7 are controlled by the following registers: IODir, IOState, IOIntEna, and IOControl. The state of CD, RI, DSR pins will not be reflected in MSR[7:5] or MSR[3:1], and any change of state on these three pins will not trigger a modem status interrupt (even if enabled via IER[3]), and the state of the DTR pin cannot be controlled by MCR[0]. As modem CD, RI, DSR pins, the status at the input of these three pins can be read from MSR[7:5] and MSR[3:1], and the state of DTR pin can be controlled by MCR[0]. Also, if modem status interrupt bit is enabled, IER[3], a change of state of RI, CD, DSR pins will trigger a modem interrupt. Bit[7:4] of the IODir, IOState, and IOIntEna registers will not have any effect on these three pins.
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8.20 Extra Features Control Register (EFCR)
Table 31. Bit 7 Extra Features Control Register bits description Symbol IRDA MODE Description IrDA mode 0 = IrDA SIR, 316 pulse ratio, data rate up to 115.2 kbit/s 1 = IrDA SIR, 14 pulse ratio, data rate up to 1.152 Mbit/s[1] 6 5 RTSINVER reserved invert RTS signal in RS-485 mode 0: RTS = 0 during transmission and RTS = 1 during reception 1: RTS = 1 during transmission and RTS = 0 during reception 4 RTSCON enable the transmitter to control the RTS pin 0 = transmitter does not control RTS pin 1 = transmitter controls RTS pin 3 2 TXDISABLE reserved Disable transmitter. UART does not send serial data out on the transmit pin, but the transmit FIFO will continue to receive data from host until full. Any data in the TSR will be sent out before the transmitter goes into disable state. 0: transmitter is enabled 1: transmitter is disabled 1 RXDISABLE Disable receiver. UART will stop receiving data immediately once this bit set to a 1, and any data in the TSR will be sent to the receive FIFO. User is advised not to set this bit during receiving. 0: receiver is enabled 1: receiver is disabled 0 9-BIT MODE Enable 9-bit or Multidrop mode (RS-485). 0: normal RS-232 mode 1: enables RS-485 mode
[1] For SC16IS760 only.
9. RS-485 features
9.1 Auto RS-485 RTS control
Normally the RTS pin is controlled by MCR bit 1, or if hardware flow control is enabled, the logic state of the RTS pin is controlled by the hardware flow control circuitry. EFCR register bit 4 will take the precedence over the other two modes; once this bit is set, the transmitter will control the state of the RTS pin. The transmitter automatically asserts the RTS pin (logic 0) once the host writes data to the transmit FIFO, and deasserts RTS pin (logic 1) once the last bit of the data has been transmitted. To use the auto RS-485 RTS mode the software would have to disable the hardware flow control function.
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9.2 RS-485 RTS output inversion
EFCR bit 5 reverses the polarity of the RTS pin if the UART is in auto RS-485 RTS mode. When the transmitter has data to be sent it will deasserts the RTS pin (logic 1), and when the last bit of the data has been sent out the transmitter asserts the RTS pin (logic 0).
9.3 Auto RS-485
EFCR bit 0 is used to enable the RS-485 mode (multidrop or 9-bit mode). In this mode of operation, a `master' station transmits an address character followed by data characters for the addressed `slave' stations. The slave stations examine the received data and interrupt the controller if the received character is an address character (parity bit = 1). To use the auto RS-485 mode the software would have to disable the hardware and software flow control functions.
9.3.1 Normal multidrop mode
The 9-bit Mode in EFCR (bit 0) is enabled, but not Special Character Detect (EFR bit 5). The receiver is set to Force Parity 0 (LCR[5:3] = 111) in order to detect address bytes. With the receiver initially disabled, it ignores all the data bytes (parity bit = 0) until an address byte is received (parity bit = 1). This address byte will cause the UART to set the parity error. The UART will generate a line status interrupt (IER bit 2 must be set to `1' at this time), and at the same time puts this address byte in the RX FIFO. After the controller examines the byte it must make a decision whether or not to enable the receiver; it should enable the receiver if the address byte addresses its ID address, and must not enable the receiver if the address byte does not address its ID address. If the controller enables the receiver, the receiver will receive the subsequent data until being disabled by the controller after the controller has received a complete message from the `master' station. If the controller does not disable the receiver after receiving a message from the `master' station, the receiver will generate a parity error upon receiving another address byte. The controller then determines if the address byte addresses its ID address, if it is not, the controller then can disable the receiver. If the address byte addresses the `slave' ID address, the controller take no further action, the receiver will receive the subsequent data.
9.3.2 Auto address detection
If Special Character Detect is enabled (EFR[5] is set and the XOFF2 register contains the address byte) the receiver will try to detect an address byte that matches the programmed character in the XOFF2 register. If the received byte is a data byte or an address byte that does not match the programmed character in the XOFF2 register, the receiver will discard these data. Upon receiving an address byte that matches the Xoff2 character, the receiver will be automatically enabled if not already enabled, and the address character is pushed into the RX FIFO along with the parity bit (in place of the parity error bit). The receiver also generates a line status interrupt (IER[2] must be set to `1' at this time). The receiver will then receive the subsequent data from the `master' station until being disabled by the controller after having received a message from the `master' station. If another address byte is received and this address byte does not match Xoff2 character, the receiver will be automatically disabled and the address byte is ignored. If the address byte matches Xoff2 character, the receiver will put this byte in the RX FIFO along with the parity bit in the parity error bit (LSR bit 2).
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10. I2C-bus operation
The two lines of the I2C-bus are a serial data line (SDA) and a serial clock line (SCL). Both lines are connected to a positive supply via a pull-up resistor, and remain HIGH when the bus is not busy. Each device is recognized by a unique address whether it is a microcomputer, LCD driver, memory or keyboard interface and can operate as either a transmitter or receiver, depending on the function of the device. A device generating a message or data is a transmitter, and a device receiving the message or data is a receiver. Obviously, a passive function like an LCD driver could only be a receiver, while a microcontroller or a memory can both transmit and receive data.
10.1 Data transfers
One data bit is transferred during each clock pulse (see Figure 16). The data on the SDA line must remain stable during the HIGH period of the clock pulse in order to be valid. Changes in the data line at this time will be interpreted as control signals. A HIGH-to-LOW transition of the data line (SDA) while the clock signal (SCL) is HIGH indicates a START condition, and a LOW-to-HIGH transition of the SDA while SCL is HIGH defines a STOP condition (see Figure 17). The bus is considered to be busy after the START condition and free again at a certain time interval after the STOP condition. The START and STOP conditions are always generated by the master.
SDA
SCL data line stable; data valid change of data allowed
mba607
Fig 16. Bit transfer on the I2C-bus
SDA
SDA
SCL S START condition P STOP condition
SCL
mba608
Fig 17. START and STOP conditions
The number of data bytes transferred between the START and STOP condition from transmitter to receiver is not limited. Each byte, which must be eight bits long, is transferred serially with the most significant bit first, and is followed by an acknowledge bit (see Figure 18). The clock pulse related to the acknowledge bit is generated by the master. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, while the transmitting device releases this pulse (see Figure 19).
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acknowledgement signal from receiver SDA MSB
SCL
S START condition
0
1
6
7
8 ACK
0
1
2 to 7
8 ACK
P STOP condition
002aab012
byte complete, interrupt within receiver
clock line held LOW while interrupt is serviced
Fig 18. Data transfer on the I2C-bus
data output by transmitter
transmitter stays off of the bus during the acknowledge clock
data output by receiver
acknowledgement signal from receiver
SCL from master
S START condition
0
1
6
7
8
002aab013
Fig 19. Acknowledge on the I2C-bus
A slave receiver must generate an acknowledge after the reception of each byte, and a master must generate one after the reception of each byte clocked out of the slave transmitter. There are two exceptions to the `acknowledge after every byte' rule. The first occurs when a master is a receiver: it must signal an end of data to the transmitter by not signalling an acknowledge on the last byte that has been clocked out of the slave. The acknowledge related clock, generated by the master should still take place, but the SDA line will not be pulled down. In order to indicate that this is an active and intentional lack of acknowledgement, we shall term this special condition as a `negative acknowledge'. The second exception is that a slave will send a negative acknowledge when it can no longer accept additional data bytes. This occurs after an attempted transfer that cannot be accepted.
10.2 Addressing and transfer formats
Each device on the bus has its own unique address. Before any data is transmitted on the bus, the master transmits on the bus the address of the slave to be accessed for this transaction. A well-behaved slave with a matching address, if it exists on the network, should of course acknowledge the master's addressing. The addressing is done by the first byte transmitted by the master after the START condition.
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An address on the network is seven bits long, appearing as the most significant bits of the address byte. The last bit is a direction (R/W) bit. A `0' indicates that the master is transmitting (write) and a `1' indicates that the master requests data (read). A complete data transfer, comprised of an address byte indicating a `write' and two data bytes is shown in Figure 20.
SDA
SCL
S START condition
0 to 6 address
7 R/W
8 ACK
0 to 6 data
7
8 ACK
0 to 6 data
7
8 ACK
P STOP condition
002aab046
Fig 20. A complete data transfer
When an address is sent, each device in the system compares the first seven bits after the START with its own address. If there is a match, the device will consider itself addressed by the master, and will send an acknowledge. The device could also determine if in this transaction it is assigned the role of a slave receiver or slave transmitter, depending on the R/W bit. Each node of the I2C-bus network has a unique seven-bit address. The address of a microcontroller is of course fully programmable, while peripheral devices usually have fixed and programmable address portions. When the master is communicating with one device only, data transfers follow the format of Figure 20, where the R/W bit could indicate either direction. After completing the transfer and issuing a STOP condition, if a master would like to address some other device on the network, it could start another transaction by issuing a new START. Another way for a master to communicate with several different devices would be by using a `repeated START'. After the last byte of the transaction was transferred, including its acknowledge (or negative acknowledge), the master issues another START, followed by address byte and data--without effecting a STOP. The master may communicate with a number of different devices, combining `reads' and `writes'. After the last transfer takes place, the master issues a STOP and releases the bus. Possible data formats are demonstrated in Figure 21. Note that the repeated START allows for both change of a slave and a change of direction, without releasing the bus. We shall see later on that the change of direction feature can come in handy even when dealing with a single device. In a single master system, the repeated START mechanism may be more efficient than terminating each transfer with a STOP and starting again. In a multimaster environment, the determination of which format is more efficient could be more complicated, as when a master is using repeated STARTs it occupies the bus for a long time and thus preventing other devices from initiating transfers.
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data transferred (n bytes + acknowledge) master write: S SLAVE ADDRESS W A DATA A DATA A P
START condition
write
acknowledge
acknowledge
acknowledge STOP condition
data transferred (n bytes + acknowledge) master read: S SLAVE ADDRESS R A DATA A DATA NA P
START condition
read
acknowledge
acknowledge
not acknowledge STOP condition
data transferred (n bytes + acknowledge) combined formats: S SLAVE ADDRESS R/W A DATA A Sr SLAVE ADDRESS R/W A
data transferred (n bytes + acknowledge) DATA A P
START condition
read or write
acknowledge
acknowledge
repeated START condition
read or write
acknowledge
acknowledge STOP condition
002aab458
direction of transfer may change at this point
Fig 21. I2C-bus data formats
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10.3 Addressing
Before any data is transmitted or received, the master must send the address of the receiver via the SDA line. The first byte after the START condition carries the address of the slave device and the read/write bit. Table 32 shows how the SC16IS740/750/760's address can be selected by using A1 and A0 pins. For example, if these 2 pins are connected to VDD, then the SC16IS740/750/760's address is set to 0x90, and the master communicates with it through this address.
Table 32. A1 VDD VDD VDD VDD VSS VSS VSS VSS SCL SCL SCL SCL SDA SDA SDA SDA
[1]
SC16IS740/750/760 address map A0 VDD VSS SCL SDA VDD VSS SCL SDA VDD VSS SCL SDA VDD VSS SCL SDA SC16IS750/760 I2C addresses (hex)[1] 0x90 (1001 000X) 0x92 (1001 001X) 0x94 (1001 010X) 0x96 (1001 011X) 0x98 (1001 100X) 0x9A (1001 101X) 0x9C (1001 110X) 0x9E (1001 111X) 0xA0 (1010 000X) 0xA2 (1010 001X) 0xA4 (1010 010X) 0xA6 (1010 011X) 0xA8 (1010 100X) 0xAA (1010 101X) 0xAC (1010 110X) 0xAE (1010 111X)
X = logic 0 for write cycle; X = logic 1 for read cycle.
10.4 Use of subaddresses
When a master communicates with the SC16IS740/750/760 it must send a subaddress in the byte following the slave address byte. This subaddress is the internal address of the word the master wants to access for a single byte transfer, or the beginning of a sequence of locations for a multi-byte transfer. A subaddress is an 8-bit byte. Unlike the device address, it does not contain a direction (R/W) bit, and like any byte transferred on the bus it must be followed by an acknowledge. Table 33 shows the breakdown of the subaddress (register address) byte. Bit 0 is not used, bits [2:1] are both set to zeroes, bits [6:3] are used to select one of the device's internal registers, and bit 7 is not used. A register write cycle is shown in Figure 22. The START is followed by a slave address byte with the direction bit set to `write', a subaddress byte, a number of data bytes, and a STOP signal. The subaddress indicates which register the master wants to access, and the data bytes which follow will be written one after the other to the subaddress location.
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Table 33 and Table 34 show the bits' presentation at the subaddress byte for I2C-bus and SPI interfaces. Bit 0 is not used, bits 2:1 select the channel, bits 6:3 select one of the UART internal registers. Bit 7 is not used with the I2C-bus interface, but it is used by the SPI interface to indicate a read or a write operation.
S
SLAVE ADDRESS
W
A
REGISTER ADDRESS(1)
A
nDATA
A
P
002aab047
White block: host to SC16IS740/750/760 Grey block: SC16IS740/750/760 to host (1) See Table 33 for additional information.
Fig 22. Master writes to slave
The register read cycle (see Figure 23) commences in a similar manner, with the master sending a slave address with the direction bit set to `write' with a following subaddress. Then, in order to reverse the direction of the transfer, the master issues a repeated START followed again by the device address, but this time with the direction bit set to `read'. The data bytes starting at the internal subaddress will be clocked out of the device, each followed by a master-generated acknowledge. The last byte of the read cycle will be followed by a negative acknowledge, signalling the end of transfer. The cycle is terminated by a STOP signal.
S
SLAVE ADDRESS
W
A
REGISTER ADDRESS(1)
A
S
SLAVE ADDRESS
R
A
nDATA
A
LAST DATA
NA
P
002aab048
White block: host to SC16IS740/750/760 Grey block: SC16IS740/750/760 to host (1) See Table 33 for additional information.
Fig 23. Master read from slave Table 33. Bit 7 6:3 2:1 0 Register address byte (I2C) Name A[3:0] CH1, CH0 Function not used UART's internal register select channel select: CH1 = 0, CH0 = 0 Other values are reserved and should not be used. not used
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Product data sheet Rev. 06 -- 13 May 2008
(c) NXP B.V. 2008. All rights reserved. SC16IS740_750_760_6
11. SPI operation
NXP Semiconductors
SCLK SI R/W A3 A2 A1 A0 CH1 CH0 X D7 D6 D5 D4 D3 D2 D1 D0
002aab433
R/W = 0; A[3:0] = register address; CH1 = 0, CH0 = 0
a. Register write
SCLK SI SO R/W A3 A2 A1 A0 CH1 CH0 X D7 D6 D5 D4 D3 D2 D1 D0
002aab434
R/W = 1; A[3:0] = register address; CH1 = 0, CH0 = 0
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
b. Register read
SCLK SI R/W A3 A2 A1 A0 CH1 CH0 X D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 last bit(1)
002aab435
R/W = 0; A[3:0] = 0000; CH1 = 0, CH0 = 0
c. FIFO write cycle
SCLK SI SO R/W A3 A2 A1 A0 CH1 CH0 X D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 last bit(2)
002aab436
SC16IS740/750/760
R/W = 1; A[3:0] = 0000; CH1 = 0, CH0 = 0
d. FIFO read cycle
(1) Last bit (D0) of the last byte to be written to the transmit FIFO. (2) Last bit (D0) of the last byte to be read from the receive FIFO.
43 of 62
Fig 24. SPI operation
NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
Register address byte (SPI) Name R/W A[3:0] CH1, CH0 Function 1: read from UART 0: write to UART UART's internal register select channel select: CH1 = 0, CH0 = 0 Other values are reserved and should not be used. not used
Table 34. Bit 7 6:3 2:1 0
12. Limiting values
Table 35. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VI II IO Ptot P/out Tamb Parameter supply voltage input voltage input current output current total power dissipation power dissipation per output ambient temperature operating VDD = 2.5 V 0.2 V VDD = 3.3 V 0.3 V Tj Tstg
[1]
Conditions any input any input any output
Min -0.3 -0.3 -10 -10 -
Max +4.6 +5.5[1] +10 +10 300 50
Unit V V mA mA mW mW
-40 -40 -65
+85 +95 +125 +150
C C C C
junction temperature storage temperature
5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 4.6 V steady state voltage tolerance on inputs and outputs when no supply voltage is present.
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Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
13. Static characteristics
Table 36. Static characteristics VDD = 2.5 V 0.2 V, Tamb = -40 C to +85 C; or VDD = 3.3 V 0.3 V, Tamb = -40 C to +95 C; unless otherwise specified. Symbol Supplies VDD IDD VIH VIL IL Ci VOH VOL Co VIH VIL VOH VOL IL Co VOL Co I2C-bus VIH VIL VOL IL Co supply voltage supply current HIGH-level input voltage LOW-level input voltage leakage current input capacitance HIGH-level output voltage LOW-level output voltage output capacitance HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage leakage current output capacitance LOW-level output voltage output capacitance input/output SDA HIGH-level input voltage LOW-level input voltage LOW-level output voltage leakage current output capacitance IOL = 1.6 mA IOL = 4 mA input; VI = 0 V or 5.5 V[1] 1.6 5.5[1] 0.6 0.4 10 7 2.0 5.5[1] 0.8 0.4 10 7 V V V V A pF IOL = 1.6 mA IOL = 4 mA IOH = -400 A IOH = -4 mA IOL = 1.6 mA IOL = 4 mA input; VI = 0 V or 5.5 V[1] IOH = -400 A IOH = -4 mA IOL = 1.6 mA IOL = 4 mA Inputs/outputs GPIO0 to GPIO7 (SC16IS750 and SC16IS760 only) 1.6 1.85 5.5[1] 0.6 0.4 1 4 0.4 4 2.0 2.4 5.5[1] 0.8 0.4 1 4 0.4 4 V V V V V V A pF V V pF input; VI = 0 V or 5.5 V[1] operating; no load 2.3 1.6 1.85 2.7 6.0 5.5[1] 0.6 1 3 0.4 4 3.0 2.0 2.4 3.6 6.0 5.5[1] 0.8 1 3 0.4 4 V mA V V A pF V V V V pF Parameter Conditions VDD = 2.5 V Min Max VDD = 3.3 V Min Max Unit
Inputs I2C/SPI, RX, CTS
Outputs TX, RTS, SO
Output IRQ
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SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
Table 36. Static characteristics ...continued VDD = 2.5 V 0.2 V, Tamb = -40 C to +85 C; or VDD = 3.3 V 0.3 V, Tamb = -40 C to +95 C; unless otherwise specified. Symbol I2C-bus VIH VIL IL Ci VIH VIL IL Ci IDD(sleep)
[1] [2]
Parameter inputs SCL, CS/A0, SI/A1 HIGH-level input voltage LOW-level input voltage leakage current input capacitance XTAL1[2] HIGH-level input voltage LOW-level input voltage leakage current input capacitance sleep mode supply current
Conditions
VDD = 2.5 V Min 1.6 Max 5.5[1] 0.6 10 7 5.5[1] 0.45 +30 3 30
VDD = 3.3 V Min 2.0 2.4 -30 Max 5.5[1] 0.8 10 7 5.5[1] 0.6 +30 3 30
Unit
V V A pF V V A pF A
input; VI = 0 V or 5.5 V[1]
1.8 -
Clock input
input; VI = 0 V or 5.5
V[1]
-30 -
Sleep current inputs are at VDD or ground -
5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 3.8 V steady state voltage tolerance on inputs and outputs when no supply voltage is present. XTAL2 should be left open when XTAL1 is driven by an external clock.
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NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
14. Dynamic characteristics
Table 37. I2C-bus timing specifications[1] All the timing limits are valid within the operating supply voltage, ambient temperature range and output load; VDD = 2.5 V 0.2 V, Tamb = -40 C to +85 C; or VDD = 3.3 V 0.3 V, Tamb = -40 C to +95 C; and refer to VIL and VIH with an input voltage of VSS to VDD. All output load = 25 pF, except SDA output load = 400 pF. Symbol Parameter Conditions Standard mode I2C-bus Min fSCL tBUF tHD;STA tSU;STA tSU;STO tHD;DAT tVD;ACK tVD;DAT tSU;DAT tLOW tHIGH tf tr tSP td1 td2 td3 td4 td5 td6 td7 td8 td15 tw(rst)
[1] [2] [3] [4]
Fast mode I2C-bus Min 0 1.3 0.6 0.6 0.6 0 150 1.3 0.6 0.5 0.2 0.2 0.2 0.2 0.2 0.2 0.5 3 3 Max 400 0.6 0.6 300 300 50 -
Unit
Max 100 0.6 0.6 300 1000 50 -
SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition set-up time for a repeated START condition set-up time for STOP condition data hold time data valid acknowledge time data valid time data set-up time LOW period of the SCL clock HIGH period of the SCL clock fall time of both SDA and SCL signals rise time of both SDA and SCL signals pulse width of spikes that must be suppressed by the input filter I2C-bus GPIO output valid time I2C-bus I2C-bus modem input interrupt valid time modem input interrupt clear time SCL LOW to data out valid
[2]
0 4.7 4.0 4.7 4.7 0 250 4.7 4.0 -
kHz s s s s ns s ns ns s s ns ns ns s s s s s s s s s s
[3]
0.5 0.2 0.2 0.2 0.2 0.2 0.2 1.0
I2C input pin interrupt valid time I2C input pin interrupt clear time I2C-bus I2C-bus I2C-bus receive interrupt valid time receive interrupt clear time transmit interrupt clear time
[4]
SCL delay time after reset reset pulse width
3 3
A detailed description of the I2C-bus specification, with applications, is given in user manual UM10204: "I2C-bus specification and user manual". This may be found at www.nxp.com/acrobat_download/usermanuals/UM10204_3.pdf. Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if SDA is held LOW for a minimum of 25 ms. Only applicable to the SC16IS750 and SC16IS760. 2 XTAL1 clocks or 3 s, whichever is less.
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Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
RESET tw(rst) SCL
002aab437
td15
Fig 25. SCL delay after reset
protocol
START condition (S) tSU;STA
bit 7 MSB (A7) tLOW tHIGH
bit 6 (A6)
bit 0 LSB (R/W)
acknowledge (A)
STOP condition (P)
1/f
SCL
SCL tBUF tr tf tSP
SDA
tHD;STA
tSU;DAT
tHD;DAT
tVD;DAT
tVD;ACK
tSU;STO
002aab489
Rise and fall times refer to VIL and VIH.
Fig 26. I2C-bus timing diagram
SDA
SLAVE ADDRESS
W
A
A IOSTATE REG.
A
DATA td1
A
GPIOn
002aab255
Fig 27. Write to output (SC16IS750 and SC16IS760 only)
ACK to master
SDA
SLAVE ADDRESS
W
A
A MSR REGISTER
A
S
SLAVE ADDRESS
R
A
DATA
A
IRQ td2 MODEM pin td3
002aab256
Fig 28. Modem input pin interrupt (SC16IS750 and SC16IS760 only)
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SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
ACK from slave
ACK from slave
ACK from master
SDA
SLAVE ADDRESS
W
A
A IOSTATE REG.
A
S
SLAVE ADDRESS
R
A
DATA
A
P
IRQ td4 GPIOn td5
002aab257
Fig 29. GPIO pin interrupt (SC16IS750 and SC16IS760 only)
start bit
stop bit
next start bit
RX
D0
D1
D2
D3
D4
D5
D6
D7 td6
IRQ
002aab258
Fig 30. Receive interrupt
SDA
SLAVE ADDRESS
W
A
A
RHR
A
S
SLAVE ADDRESS
R
A
DATA
A
P
IRQ td7
002aab259
Fig 31. Receive interrupt clear
SDA
SLAVE ADDRESS
W
A
ATHR REGISTER
A
DATA
A
IRQ td8
002aab260
Fig 32. Transmit interrupt clear
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Product data sheet
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NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
Table 38. fXTAL dynamic characteristics VDD = 2.5 V 0.2 V, Tamb = -40 C to +85 C; or VDD = 3.3 V 0.3 V, Tamb = -40 C to +95 C Symbol tw1 tw2 fXTAL
[1] [2]
Parameter clock pulse duration clock pulse duration frequency on pin XTAL
Conditions
VDD = 2.5 V Min 10 10
[1][2]
VDD = 3.3 V Min 6 6 Max 80
Unit ns ns MHz
Max 48
-
Applies to external clock, crystal oscillator max. 24 MHz.
1 f XTAL = ------t w3
tw2 EXTERNAL CLOCK tw3
tw1
002aaa112
Fig 33. External clock timing Table 39. SC16IS740/750 SPI-bus timing specifications All the timing limits are valid within the operating supply voltage, ambient temperature range and output load; VDD = 2.5 V 0.2 V, Tamb = -40 C to +85 C; or VDD = 3.3 V 0.3 V, Tamb = -40 C to +95 C; and refer to VIL and VIH with an input voltage of VSS to VDD. All output load = 25 pF, unless otherwise specified. Symbol tTR tCSS tCSH tDO tDS tDH tCP tCH tCL tCSW td9 td10 td11 td12 td13 td14 tw(rst) Parameter CS HIGH to SO 3-state delay time CS to SCLK setup time CS to SCLK hold time SCLK fall to SO valid delay time SI to SCLK setup time SI to SCLK hold time SCLK period SCLK HIGH time SCLK LOW time CS HIGH pulse width SPI output data valid time SPI modem output data valid time SPI transmit interrupt clear time SPI modem input interrupt clear time SPI interrupt clear time SPI receive interrupt clear time reset pulse width tCL + tCH CL = 100 pF Conditions CL = 100 pF Min 100 20 100 20 250 100 100 200 200 200 200 200 200 200 3 Typ Max 100 100 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s
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NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
Table 40. SC16IS760 SPI-bus timing specifications All the timing limits are valid within the operating supply voltage, ambient temperature range and output load; VDD = 2.5 V 0.2 V, Tamb = -40 C to +85 C; or VDD = 3.3 V 0.3 V, Tamb = -40 C to +95 C and refer to VIL and VIH with an input voltage of VSS to VDD. All output load = 25 pF, unless otherwise specified. Symbol tTR tCSS tCSH tDO tDS tDH tCP tCH tCL tCSW td9 td10 td11 td12 td13 td14 tw(rst) Parameter CS HIGH to SO 3-state delay time CS to SCLK setup time CS to SCLK hold time SCLK fall to SO valid delay time SI to SCLK setup time SI to SCLK hold time SCLK period SCLK HIGH time SCLK LOW time CS HIGH pulse width SPI output data valid time SPI modem output data valid time SPI transmit interrupt clear time SPI modem input interrupt clear time SPI interrupt clear time SPI receive interrupt clear time reset pulse width tCL + tCH CL = 100 pF Conditions CL = 100 pF 100 5 10 10 83 30 30 200 200 200 200 200 200 200 3 VDD = 2.5 V Min 25 Max 100 100 5 10 10 67 25 25 200 200 200 200 200 200 200 3 VDD = 3.3 V Min 20 Max 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s Unit
CS tCSH tCL tCH tCSH tCSW
tCSS
SCLK tDH tDS SI tDO SO
002aab066
tTR
Fig 34. Detailed SPI-bus timing
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Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
CS SCLK SI GPIOx
002aab438
R/W
A3
A2
A1
A0
CH1 CH0
X
D7
D6
D5
D4
D3
D2
D1
D0 td9
R/W = 0; A[3:0] = IOState (0x0B); CH1 = 0; CH0 = 0
Fig 35. SPI write IOState to GPIO switch (SC16IS750 and SC16IS760 only)
CS SCLK SI DTR (GPIO5)
002aab439
R/W
A3
A2
A1
A0
CH1 CH0
X
D7
D6
D5
D4
D3
D2
D1
D0 td10
R/W = 0; A[3:0] = MCR (0x04); CH1 = 0; CH0 = 0
Fig 36. SPI write MCR to DTR output switch (SC16IS750 and SC16IS760 only)
CS SCLK SI SO td11 IRQ
002aab440
R/W
A3
A2
A1
A0
CH1 CH0
X
D7
D6
D5
D4
D3
D2
D1
D0
R/W = 0; A[3:0] = THR (0x00); CH1 = 0; CH0 = 0
Fig 37. SPI write THR to clear TX INT
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Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
CS SCLK SI SO td12 IRQ
002aab441
R/W
A3
A2
A1
A0
CH1 CH0
X D7 D6 D5 D4 D3 D2 D1 D0
R/W = 1; A[3:0] = MSR (0x06); CH1 = 0; CH0 = 0
Fig 38. Read MSR to clear modem INT (SC16IS750 and SC16IS760 only)
CS SCLK SI SO td13 IRQ
002aab442
R/W
A3
A2
A1
A0
CH1 CH0
X D7 D6 D5 D4 D3 D2 D1 D0
R/W = 1; A[3:0] = IOState (0x0B); CH1 = 0; CH0 = 0
Fig 39. Read IOState to clear GPIO INT (SC16IS750 and SC16IS760 only)
CS SCLK SI SO td14 IRQ
002aab443
R/W
A3
A2
A1
A0
CH1 CH0
X D7 D6 D5 D4 D3 D2 D1 D0
R/W = 1; A[3:0] = RHR (0x00); CH1 = 0; CH0 = 0
Fig 40. Read RHR to clear RX INT
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Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
15. Package outline
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
D
E
A
X
c y HE vMA
Z
16
9
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
8
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18
Fig 41. Package outline SOT403-1 (TSSOP16)
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SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm
SOT616-3
D
B
A
terminal 1 index area A A1 E c
detail X
e1
1/2 e
C b 12 vMCAB wMC 13 y1 C y
e 7 L 6
e
Eh
1/2 e
e2
1 18 terminal 1 index area
24 Dh 0
19 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 4.1 3.9 Dh 2.75 2.45 E (1) 4.1 3.9 Eh 2.75 2.45 e 0.5 e1 2.5 e2 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT616-3 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 04-11-19 05-03-10
Fig 42. Package outline SOT616-3 (HVQFN24)
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Product data sheet
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NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
D
E
A
X
c y HE vMA
Z
24
13
Q A2 pin 1 index A1 (A 3) A
Lp L
1
e bp
12
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 7.9 7.7 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 8o 0o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT355-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19
Fig 43. Package outline SOT355-1 (TSSOP24)
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Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
16. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling integrated circuits.
17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
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Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities 17.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 44) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 41 and 42
Table 41. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 42. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 44.
SC16IS740_750_760_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 13 May 2008
58 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 44. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
18. Abbreviations
Table 43. Acronym CPU FIFO GPIO I2C-bus IrDA LCD MIR POR SIR SPI UART Abbreviations Description Central Processing Unit First In, First Out General Purpose Input/Output Inter IC bus Infrared Data Association Liquid Crystal Display Medium InfraRed Power-On Reset Serial InfraRed Serial Peripheral Interface Universal Asynchronous Receiver/Transmitter
SC16IS740_750_760_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 13 May 2008
59 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
19. Revision history
Table 44. Revision history Release date 20080513 Data sheet status Product data sheet Change notice Supersedes SC16IS740_750_760_5 Document ID SC16IS740_750_760_6 Modifications:
* *
Figure 24 "SPI operation" updated; added Figure note [1] and Figure note [2] Table 37 "I2C-bus timing specifications[1]": - added specification tw(rst) - updated Table note [1] - Table note [4]: changed from "X1" to "XTAL1"
* * * *
Figure 25 "SCL delay after reset" updated; added timing tw(rst) Table 39 "SC16IS740/750 SPI-bus timing specifications" updated; added specification tw(rst) Figure 34 "Detailed SPI-bus timing" updated; adjusted timing tCSH Table 40 "SC16IS760 SPI-bus timing specifications": - added specification tw(rst) - tCSH(min) changed from "20 ns" to "5 ns" (for both 2.5 V and 3.3 V VDD voltages)
*
SC16IS740_750_760_5 SC16IS740_750_760_4 SC16IS740_750_760_3 SC16IS740_750_760_2 SC16IS740_750_760_1 (9397 750 14832)
updated SMD package soldering information Product data sheet Product data sheet Product data sheet Product data sheet Product data sheet SC16IS740_750_760_4 SC16IS740_750_760_3 SC16IS740_750_760_2 SC16IS740_750_760_1 -
20061116 20061030 20060522 20060330 20060104
SC16IS740_750_760_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 13 May 2008
60 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
20. Legal information
20.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
20.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
21. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
SC16IS740_750_760_6
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 -- 13 May 2008
61 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
22. Contents
1 2 2.1 2.2 2.3 3 4 5 6 6.1 6.2 7 7.1 7.2 7.2.1 7.2.2 7.3 7.3.1 7.3.2 7.4 7.5 7.5.1 7.5.2 7.6 7.7 7.8 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General features . . . . . . . . . . . . . . . . . . . . . . . . 1 I2C-bus features . . . . . . . . . . . . . . . . . . . . . . . . 2 SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional description . . . . . . . . . . . . . . . . . . . 9 Trigger levels. . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Hardware flow control . . . . . . . . . . . . . . . . . . . . 9 Auto RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Auto CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Software flow control . . . . . . . . . . . . . . . . . . . 11 RX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Hardware reset, Power-On Reset (POR) and software reset . . . . . . . . . . . . . . . . . . . . . . . . . 14 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Interrupt mode operation . . . . . . . . . . . . . . . . 16 Polled mode operation . . . . . . . . . . . . . . . . . . 16 Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Break and time-out conditions . . . . . . . . . . . . 17 Programmable baud rate generator . . . . . . . . 17 Register descriptions . . . . . . . . . . . . . . . . . . . 20 Receive Holding Register (RHR) . . . . . . . . . . 23 Transmit Holding Register (THR) . . . . . . . . . . 23 FIFO Control Register (FCR) . . . . . . . . . . . . . 23 Line Control Register (LCR) . . . . . . . . . . . . . . 24 Line Status Register (LSR) . . . . . . . . . . . . . . . 26 Modem Control Register (MCR) . . . . . . . . . . . 27 Modem Status Register (MSR). . . . . . . . . . . . 28 Interrupt Enable Register (IER) . . . . . . . . . . . 29 Interrupt Identification Register (IIR). . . . . . . . 30 Enhanced Features Register (EFR) . . . . . . . . 31 Division registers (DLL, DLH) . . . . . . . . . . . . . 31 Transmission Control Register (TCR) . . . . . . . 32 Trigger Level Register (TLR). . . . . . . . . . . . . . 32 Transmitter FIFO Level register (TXLVL) . . . . 32 Receiver FIFO Level register (RXLVL) . . . . . . 33 Programmable I/O pins Direction register (IODir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.17 8.18 8.19 8.20 9 9.1 9.2 9.3 9.3.1 9.3.2 10 10.1 10.2 10.3 10.4 11 12 13 14 15 16 17 17.1 17.2 17.3 17.4 18 19 20 20.1 20.2 20.3 20.4 21 22 Programmable I/O pins State Register (IOState). . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Interrupt Enable Register (IOIntEna) . . . . I/O Control register (IOControl) . . . . . . . . . . . Extra Features Control Register (EFCR) . . . . RS-485 features . . . . . . . . . . . . . . . . . . . . . . . . Auto RS-485 RTS control. . . . . . . . . . . . . . . . RS-485 RTS output inversion. . . . . . . . . . . . . Auto RS-485. . . . . . . . . . . . . . . . . . . . . . . . . . Normal multidrop mode . . . . . . . . . . . . . . . . . Auto address detection. . . . . . . . . . . . . . . . . . 2C-bus operation . . . . . . . . . . . . . . . . . . . . . . I Data transfers. . . . . . . . . . . . . . . . . . . . . . . . . Addressing and transfer formats . . . . . . . . . . Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . Use of subaddresses . . . . . . . . . . . . . . . . . . . SPI operation . . . . . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Handling information . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 33 34 35 35 35 36 36 36 36 37 37 38 41 41 43 44 45 47 54 57 57 57 57 57 58 59 60 61 61 61 61 61 61 62
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 13 May 2008 Document identifier: SC16IS740_750_760_6

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